Semiconductor chips are used in a wide variety of electronic devices. A semiconductor chip is a small, often very small piece of a semiconductor material upon which various electric components have been fabricated and connected together to form integrated circuits. These circuits perform a variety of functions, such as memory or processing, in support of the semiconductor chip's role in the electronic device.
To form these circuits, the fabrication process typically begins with providing a substrate formed, for example, of silicon. The substrate material is usually sliced into a round, flat shape often called a wafer. A number of chips will typically be fabricated onto a single wafer. The surface of the wafer substrate is selectively treated with boron or phosphorus ions to impart the semiconductor characteristics. Insulating and conducting materials of various types are then layered onto the surface and formed into various shapes, for example by etching, to build small electrical such as transistors and capacitors and to connect those components to, or isolate them from each other.
These small components are frequently built in a series of steps, each of which deals with one or more of the layered materials referred to above and shapes them into one or more features. In a given step, however, many features are formed on the wafer surface, each feature being a part of one (or perhaps more) of the electrical components. These features are often arranged in an orderly fashion on the wafer surface, this arrangement being referred to as a layout. The layout takes into account the number of such features that will be required as well as how the components they are part of will eventually interconnect in order to function together. The designed layout, of course, attempts to make the most efficient use possible of the wafer surface. Millions of electronic components are formed on the wafer, which is typically cut up into a number of dice. Each die is then configured with appropriate external leads and encapsulated in a plastic package for use.
As mentioned above, a great number of features may be formed simultaneously on the wafer surface, although forming these features may itself require a number of process steps. One such process involves photolithography, and the subsequent selective etching of the wafer surface. (Note that as used herein, ‘wafer surface’ includes the topmost (outer) layer, or sometimes layers of the wafer involved in the fabrication. This may be but is not necessarily the surface of the substrate itself.) Lithography involves depositing a layer of material called photoresist (or simply ‘resist’) onto the wafer surface. When exposed to light, this resist changes properties, becoming either easier or harder to remove (depending on the type of resist used) in a subsequent solvent wash step. This is a useful process, because patterns of resist may be created by selective exposure to some form of light energy.
To create patterns on the resist layer that has been deposited onto the wafer surface, certain selected portions of it are exposed to light energy. To control the exposure, a mask is used. A mask is a typically flat plate forming a number of openings or transparent or translucent portions through which light may pass. Note that as used herein, the term ‘mask’ is intended to include a reticle or portions of a mask that illuminate only a portion of the wafer surface at any given time. Once the wafer surface has been selectively exposed using the mask, a solvent wash is used to remove unwanted portions of the resist and leave behind a pattern of resist structures.
An inspection may be performed at this stage to ensure that the resist structures have been properly formed. In any case, after the resist is patterned, a dry or wet etch step may then be used to remove portions of the wafer surface not protected by the resist, forming a recess or leaving a structure of the desired configuration. Some lateral etching of the walls of a recess to extend it somewhat may also occur, and this phenomenon may in fact be intended. The extent of the material etched away may be controlled by the type of etching agent used and the amount of time the wafer surface is exposed to it. If the photoresist structures are not needed for a subsequent step, for example further ion implantation, or following such a step, they are removed using an appropriate solvent. The desired features remain and the fabrication process continues.
Technological advances have permitted the formation of ever smaller electrical components, placed closer and closer together on the wafer surface. This can be of great commercial advantage because it permits the chips to be used in very capable devices that are nevertheless quite small. This trend has enabled, for example, the development of convenient personal computers, laptops, cell phones, and portable digital music players. The continuing demand for new and better devices has created industry pressure to fabricate even smaller and more powerful devices. This means that the electronic components formed on the wafer surface must get even smaller in size and be situated even more closely together.
This drive to smaller components and more dense layouts poses challenges for photolithography. As the size of the desired features becomes closer to the wavelength of the light used for exposure, optical effects such as diffraction may cause deformation of the surface structures. The increased density of the layout may also lead to the occurrence of proximity effects for similar reasons. Line shortening and corner rounding are examples of such deformation. Where such imperfections may not have had as significant impact on larger features, the performance of very small features may degrade unacceptably.
To counter these problems, various resolution enhancement techniques (RETs) have been developed. One of these techniques is optical proximity correction (OPC). OPC takes into account the proposed layout for electrical components on the wafer and determines how the mask might be altered to created the desired features. In other words, the mask is altered to ameliorate or eliminate the optical effects due to small component size or increased density. The size and shape of the mask openings may be, for example, adjusted, or sub-resolution assist features (SRAFs) strategically added. An SRAF is a mask opening that is too small to result in the creation of a corresponding feature on the surface, given the wavelength of light being used, but large enough alter the optical effects mentioned above, resulting in features that are more-properly formed.
The OPC process described above may vary, and the process is somewhat successful. Nevertheless, the persistent pressure for layouts with smaller components in more dense applications means that there remains a need for refinements in mask design and OPC enhancement techniques. The present invention provides just such a solution.